struct _HALP_DMA_CONTROLLER// Size=0xe0
{
    struct _LIST_ENTRY Controllers;// Offset=0x0 Size=0x10
    struct _LIST_ENTRY AdapterList;// Offset=0x10 Size=0x10
    unsigned long ControllerId;// Offset=0x20 Size=0x4
    unsigned long MinimumRequestLine;// Offset=0x24 Size=0x4
    unsigned long MaximumRequestLine;// Offset=0x28 Size=0x4
    unsigned long ChannelCount;// Offset=0x2c Size=0x4
    unsigned long ScatterGatherLimit;// Offset=0x30 Size=0x4
    struct _HALP_DMA_CHANNEL * Channels;// Offset=0x38 Size=0x8
    void * ExtensionData;// Offset=0x40 Size=0x8
    unsigned char CacheCoherent;// Offset=0x48 Size=0x1
    unsigned long DmaAddressWidth;// Offset=0x4c Size=0x4
    struct _DMA_FUNCTION_TABLE Operations;// Offset=0x50 Size=0x50
    unsigned long SupportedPortWidths;// Offset=0xa0 Size=0x4
    unsigned long MinimumTransferUnit;// Offset=0xa4 Size=0x4
    unsigned long long Lock;// Offset=0xa8 Size=0x8
    unsigned char Irql;// Offset=0xb0 Size=0x1
    unsigned char GeneratesInterrupt;// Offset=0xb1 Size=0x1
    long Gsi;// Offset=0xb4 Size=0x4
    enum _KINTERRUPT_POLARITY InterruptPolarity;// Offset=0xb8 Size=0x4
    enum _KINTERRUPT_MODE InterruptMode;// Offset=0xbc Size=0x4
    struct _UNICODE_STRING ResourceId;// Offset=0xc0 Size=0x10
    struct POHANDLE__ * PowerHandle;// Offset=0xd0 Size=0x8
    unsigned char PowerActive;// Offset=0xd8 Size=0x1
};